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NANA SUTISNA

Institut Teknologi Bandung S1 - Teknik Informatika SINTA ID : 6755701
1.662
SINTA Score Overall
655
SINTA Score 3Yr
1.662
Affil Score
655
Affil Score 3Yr
Latest number of publications
DQN Algorithm Design for Fast Efficient Shortest Path System
WOS.ISTP Edition 2023 ASIA PACIFIC SIGNAL AND INFORMATION PROCESSING ASSOCIATION ANNUAL SUMMIT AND CONFERENCE, APSIPA ASC
Author Order: 2 of 5     Authors : Sumarudin, A; Sutisna, N; Syafalni, I; Trilaksono, BR; Adiono, T;
2023 0 cited Scopus Indexed DOI : 10.1109/APSIPAASC58517.2023.10317113
High Throughput and Low Latency Wireless Communication System using Bandwidth-Efficient Transmission for Medical Internet of Thing
WOS.ESCI Edition   Core Collection INTERNATIONAL JOURNAL OF TECHNOLOGY
Author Order: 2 of 6     Authors : Kurniawati, AM; Sutisna, N; Zakaria, H; Nagao, Y; Mengko, TL; Ochi, H;
JUN 28 2023 1 cited Scopus Indexed DOI : 10.14716/ijtech.v14i4.5234
Sparsity Exploration for Structured and Unstructured Weight Formations in CNN Architecture
WOS.ISTP Edition 2023 ASIA PACIFIC SIGNAL AND INFORMATION PROCESSING ASSOCIATION ANNUAL SUMMIT AND CONFERENCE, APSIPA ASC
Author Order: 3 of 4     Authors : Endrawati, DN; Syafalni, I; Sutisna, N; Adiono, T;
2023 0 cited Scopus Indexed DOI : 10.1109/APSIPAASC58517.2023.10317585
FARANE-Q: Fast Parallel and Pipeline Q-Learning Accelerator for Configurable Reinforcement Learning SoC
WOS.SCI Edition   Core Collection IEEE ACCESS
Author Order: 1 of 5     Authors : Sutisna, N; Ilmy, AMR; Syafalni, I; Mulyawan, R; Adiono, T;
2023 2 cited Scopus Indexed DOI : 10.1109/ACCESS.2022.3232853
Fast and Scalable Multicore YOLOv3-Tiny Accelerator Using Input Stationary Systolic Architecture
WOS.SCI Edition   Core Collection IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS
Author Order: 3 of 6     Authors : Adiono, T; Ramadhan, RM; Sutisna, N; Syafalni, I; Mulyawan, R; Lin, CH;
NOV 2023 0 cited Scopus Indexed DOI : 10.1109/TVLSI.2023.3305937
Comparison of MPPT based on Deep Reinforcement Learning by DQN, DDPG and TD3
WOS.ISTP Edition 2023 ASIA PACIFIC SIGNAL AND INFORMATION PROCESSING ASSOCIATION ANNUAL SUMMIT AND CONFERENCE, APSIPA ASC
Author Order: 2 of 4     Authors : Panggabean, J; Sutisna, N; Syafalni, I; Adiono, T;
2023 0 cited Scopus Indexed DOI : 10.1109/APSIPAASC58517.2023.10317341
A QoS Throughput Performance Measurement Comparison between UGS and BE Services of a Real-time FPGA Based OFDM Multi-user System Design Implementation
WOS.ISTP Edition 2023 ASIA PACIFIC SIGNAL AND INFORMATION PROCESSING ASSOCIATION ANNUAL SUMMIT AND CONFERENCE, APSIPA ASC
Author Order: 4 of 6     Authors : Adiono, T; Jonathan, M; Setiawan, E; Sutisna, N; Mulyawan, R; Syafalni, I;
2023 0 cited Scopus Indexed DOI : 10.1109/APSIPAASC58517.2023.10317290
MazeCov-Q: An Efficient Maze-Based Reinforcement Learning Accelerator for Coverage
WOS.ISTP Edition 2023 IEEE SYMPOSIUM IN LOW-POWER AND HIGH-SPEED CHIPS, COOL CHIPS
Author Order: 4 of 5     Authors : Syafalni, I; Firdaus, MI; Ilmy, AMR; Sutisna, N; Adiono, T;
2023 0 cited Scopus Indexed DOI : 10.1109/COOLCHIPS57690.2023.10122120
SUMO Based Hardware/Software Co-simulation for Two-Intersection Adaptive and Collaborative Traffic Signal Controller
WOS.ISTP Edition 2023 ASIA PACIFIC SIGNAL AND INFORMATION PROCESSING ASSOCIATION ANNUAL SUMMIT AND CONFERENCE, APSIPA ASC
Author Order: 2 of 4     Authors : Ginting, KE; Sutisna, N; Syafalni, I; Adiono, T;
2023 0 cited Scopus Indexed DOI : 10.1109/APSIPAASC58517.2023.10317355
Efficient Homomorphic Encryption Accelerator With Integrated PRNG Using Low-Cost FPGA
WOS.SCI Edition   Core Collection IEEE ACCESS
Author Order: 3 of 5     Authors : Syafalni, I; Jonatan, G; Sutisna, N; Mulyawan, R; Adiono, T;
2022 13 cited Scopus Indexed DOI : 10.1109/ACCESS.2022.3143804
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Summary

Article Quartile
Research Output
  Scopus GScholar WOS
Article 90 100 22
Citation 196 272 43
Cited Document 51 53 10
H-Index 6 8 3
i10-Index 4 6 2
G-Index 2 1 1
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